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ATmega128
Store Program
Memory Control and
The Store Program Memory Control and Status Register contains the control bits needed to con-
trol the Boot Loader operations.
Status Register –
SPMCSR
Bit
Read/ W rite
Initial Value
7
SPMIE
R/ W
0
6
RWWSB
R
0
5
–
R
0
4
RWWSRE
R/ W
0
3
BLBSET
R/ W
0
2
PGWRT
R/ W
0
1
PGERS
R/ W
0
0
SPMEN
R/ W
0
SPMCSR
? Bit 7 – SPMIE: SPM Interrupt Enable
W hen the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM
ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN
bit in the SPMCSR Register is cleared.
? Bit 6 – RWWSB: Read-While-Write Section Busy
W hen a Self-Programming (page erase or page write) operation to the R WW section is initiated,
the R WW SB will be set (one) by hardware. W hen the R WW SB bit is set, the R WW section can-
not be accessed. The R WW SB bit will be cleared if the R WW SRE bit is written to one after a
self-programming operation is completed. Alternatively the R WW SB bit will automatically be
cleared if a page load operation is initiated.
? Bit 5 – Res: Reserved Bit
This bit is a reserved bit in the ATmega128 and always read as zero.
? Bit 4 – RWWSRE: Read-While-Write Section Read Enable
W hen Programming (page erase or page write) to the R WW section, the R WW section is
blocked for reading (the R WW SB will be set by hardware). To re-enable the R WW section, the
user software must wait until the programming is completed (SPMEN will be cleared). Then, if
the R WW SRE bit is written to one at the same time as SPMEN, the next SPM instruction within
four clock cycles re-enables the R WW section. The R WW section cannot be re-enabled while
the Flash is busy with a page erase or a page write (SPMEN is set). If the R WW SRE bit is writ-
ten while the Flash is being loaded, the Flash load operation will abort and the data loaded will
be lost.
? Bit 3 – BLBSET: Boot Lock Bit Set
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock
cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z-
pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the lock bit
set, or if no SPM instruction is executed within four clock cycles.
An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCSR Reg-
ister, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the
destination register. See “Reading the Fuse and Lock Bits from Software” on page 281 for
details.
? Bit 2 – PGWRT: Page Write
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock
cycles executes page write, with the data stored in the temporary buffer. The page address is
taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PG W RT bit
will auto-clear upon completion of a page write, or if no SPM instruction is executed within four
clock cycles. The CPU is halted during the entire page write operation if the NR WW section is
addressed.
? Bit 1 – PGERS: Page Erase
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock
cycles executes page erase. The page address is taken from the high part of the Z-pointer. The
data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a page erase,
277
2467X–AVR–06/11
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